--
-- VHDL Architecture Reverb_lib.delay.behaviour
--
-- Created:
--          by - Siebe.UNKNOWN (SIEBJE)
--          at - 13:25:15 20-05-2008
--
-- using Mentor Graphics HDL Designer(TM) 2005.3 (Build 75)
--
library ieee;
use ieee.std_logic_signed.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity comb is
	 generic(
		delay						: integer);
	 port(
      clk						: in std_logic;
		clk_48k					: in std_logic;
      reset						: in std_logic;
		
		control_in				: in std_logic_vector(7 downto 0);
		control_out				: out std_logic_vector(3 downto 0);
		
      PCM_data_in				: in std_logic_vector(15 downto 0);
		PCM_data_out			: out std_logic_vector(15 downto 0)
      );
  end entity comb;

--
architecture behaviour of comb is
   
  component fifo_4k_16 is
	port (
		clk			: in std_logic;
		din			: in std_logic_VECTOR(15 downto 0);
		rd_en			: in std_logic;
		rst			: in std_logic;
		wr_en			: in std_logic;
		data_count	: out std_logic_VECTOR(11 downto 0);
		dout			: out std_logic_VECTOR(15 downto 0);
		empty			: out std_logic;
		full			: out std_logic
		);
	end component fifo_4k_16;
  
	signal last_48k_clock	: std_logic := '0';
	signal read_enable		: std_logic := '0';
	signal write_enable		: std_logic := '0';
	signal reset_n				: std_logic := '1';
	signal fifo_empty			: std_logic := '0';
	signal fifo_full			: std_logic := '0';
	signal data_count			: std_logic_vector(11 downto 0);
	
	signal delay_cycles		: integer	:= delay;
	signal count				: integer	:= delay;
	
	signal fifo_data_out		: std_logic_vector(15 downto 0);
	signal fifo_data_in		: std_logic_vector(15 downto 0);
	
begin
	control_out(0) 			<= fifo_full;
	control_out(1) 			<= fifo_empty;
	control_out(3 downto 2) <= "10";

	reset_n		<= not reset;

	Fifo0: fifo_4k_16 port map(	clk			=> clk_48k,			--FIFO runs on 48kHz clock  
											din			=> fifo_data_in,
											rd_en			=> read_enable,
											rst			=> reset_n,
											wr_en			=> write_enable,
											data_count	=> data_count,
											dout			=> fifo_data_out,
											empty			=> fifo_empty,
											full			=> fifo_full
										);

	Process0: process (clk_48k, reset)
	begin
		if (reset = '0') then
			PCM_data_out 	<= (others => '0');
			fifo_data_in	<= (others => '0');
			count 			<= delay;
			read_enable		<= '0';
			write_enable	<= '0';
		elsif (clk_48k'event and clk_48k = '1') then
			write_enable 	<= '1';
			read_enable 	<= '0';
			if count = 0 then
				read_enable <= '1';
			else
				count <= count - 1;
			end if;
			fifo_data_in	<= shr(PCM_data_in,"01") + shr(fifo_data_out,"010");	--g = 1/2
			PCM_data_out	<= fifo_data_out;
		end if;
	end process;
    
END ARCHITECTURE behaviour;
